1. Field of the Invention
The present invention relates to a level shift circuit mounted on a semiconductor device.
2. Background Art
A conventional level shift circuit will be described. FIG. 2 is a circuit diagram illustrating a conventional level shift circuit.
When an input voltage VIN goes to a high level, namely, a first power supply voltage VDD1, then an inverter 51 causes the gate voltage of an NMOS transistor 52 to become a ground voltage VSS. This causes the NMOS transistor 52 to turn off. Meanwhile, an NMOS transistor 53 turns on and an output voltage VOUT goes to a low level, namely, the ground voltage VSS. At this time, a PMOS transistor 54 is on, the voltage of an internal node N1 is a second power supply voltage VDD2, and a PMOS transistor 55 is off
Further, when the input voltage VIN goes to the low level, namely, the ground voltage VSS, the inverter 51 causes the gate voltage of the NMOS transistor 52 to become the first power supply voltage VDD1. Then, the NMOS transistor 52 turns on, the voltage of the internal node N1 becomes the ground voltage VSS, the PMOS transistor 55 turns on, and the output voltage VOUT goes to the high level, namely, the second power supply voltage VDD2. At this time, the NMOS transistor 53 is off (refer to, for example, Patent Document 1).
[Patent Document 1] Japanese Patent Application Laid-Open No. 2012-134690
However, according to the art disclosed in Patent Document 1, if the first power supply voltage VDD1 becomes lower than a minimum operating power supply voltage of the level shift circuit, then the circuit malfunctions, inconveniently making the output voltage VOUT unstable.